1. Field of Invention
The present invention relates to a method for producing semiconductor devices and more particularly to a method for selectively exposing the sidewalls of a trench and its use in the formation of a metal silicide substrate contact for high density dielectric filled, deep trench isolated semiconductor devices.
2. Brief Description of the Prior Art
A reverse bias is commonly applied to the substrate in a semiconductor integrated chip for isolation purposes. In this case, the potential of the substrate is maintained at an appropriate value, so that the P-N junction of the isolation region and the substrate becomes reverse biased.
Conventional methods for forming a substrate contact for a semiconductor device are well known, such as a method for forming an electrode at the backside of the substrate to which is applied an external bias. With the development of large scale integration, thick and low doped substrates are widely used. Silicon wafers have lightly doped substrates in order to significantly reduce collector-substrate capacitances, which, in turn, increase the operating frequencies of the devices. Unfortunately, when the impurity concentration of the substrate is low, the electrical path between the electrode and the substrate becomes highly resistive, resulting in active devices, such as PNP lateral transistors having poor characteristics. This problem has been eliminated by contacting the substrate, through the N type epitaxial layer, with a highly doped P region. An example of this technique, in combination with standard recessed oxide isolation, may be found in European Patent application bearing the publication number 29552 assigned to VLSI Technology Research Association.
More recent trends in micro-electronics capitalize on a particular type of dielectric isolation where patterns of dielectrically filled trenches, extending from the surface of the integrated circuit to the interior thereof are used to isolate the devices (e.g. one bipolar transistor from another bipolar transistor) or portions (e.g. the base region from the collector region in a bipolar transistor) of the devices.
A method of forming a substrate contact for a trench structure is taught in an article of the IBM Technical Disclosure Bulletin, vol. 25 No. 12, May 1983, pages 6611 through 6614, authored by S. A. Abbas et al. This article describes the formation of a polysilicon buried conductor for reach through to the P substrate for ohmic electrical contact thereto. Once the trenches and channel stoppers have been formed, and trenches protected with an insulating layer, the bottom of the trench, where a contact is needed, is opened to expose the channel stopper. A thin polysilicon layer is CVD deposited, covering the sidewalls in totality and providing a contact with the substrate. It is obvious that with this technique, the P.sup.+ substrate contact reach through is highly resistive, not suitable for advanced bipolar devices. Also, a parasitic polysilicon-oxide-silicon capacitor is created which will degrade the circuit performance.
A variant is described in U.S. Pat. No. 4,256,514 assigned to the assignee of the present invention. According to this patent, a doped, polysilicon stud is used to provide the electrical contact with the substrate. However, although doped polysilicon still remains a relatively resistive material, and this solution is not completely satisfactory, because it implies the use of wide trenches, completely filled with polysilicon to reduce the resistance of the stud, which in turn results in lower integration density.
In addition, some other problems may result from this solution, due to, firstly different thermal coefficients between polysilicon and silicon, which may lead to undesired cracks in the filled trenches and, secondly, the resulting structure has very poor planarity. Planarity is a must when multilevel metallurgy (e.g. 4) is needed to assure the fan-in, and the fan-out functions of highly integrated circuits.
An other alternate solution is described in "Plasma oxide filled deep dielectric isolation", J. S. Basi et al, IBM Technical Disclosure Bulletin, vol. 25 No. 8, Jan. 1983 pages 4405 and 4406. This article describes a method for forming a buried conductor for reach-through to the P.sup.- silicon substrate of a chip from the surface of an epitaxial layer. The substrate contact is made by shorting the subcollector to the P channel stopper, at the bottom of the trenches and then to the top metallurgy via the collector reach through diffusion. The role of the metal is therefore to short the N.sup.- epitaxy-P substrate/P.sup.+ channel stopper junction.
In this reference (and in the aforementioned U.S. Pat. No. 4,256,514 as well), a part of the electrical path, between the contact and the substrate is made of highly doped silicon material. Therefore, this solution cannot also be considered as fully satisfactory.
It is very important to remark that according to the teachings of this article, an isotropic etch is performed to expose all the sidewalls of a trench. Therefore, all devices adjacent to that trench, will have their N.sup.- epitaxy-P.sup.- substrate junction shorted by the Pt-Si contact. In others words, all these devices will be only devoted to provide substrate contact and therefore will be lost for logical implementation. This results in a non negligible waste of the silicon surface.